The present invention relates to a semiconductor integrated circuit device mounted on mobile communication equipment or the like and, more particularly, to a technology which is effective in reducing the distortion of a transmission/reception signal.
In recent years, mobile phones have developed a wide variety of services using data communication in addition to voice communication and are still continuing to evolve.
The representative frequency bands used by mobile phone services in Europe are the 900 MHz band for the GSM (Global System for Mobile Communicator) and the 1.8 GHz band for the DCS (Digital Cellular System), while the 1.9 GHz band for the PCS (Personal Communication Service) and the 850 MHz band for the GSM are used typically in the United States. In addition, the W-CDMA using the 2 GHz band has joined therein so that multiband/multimode capabilities are essential requirements for mobile terminals.
With the prevalence of such multiband/multimode mobile phones, a small-size and high-performance SPDT (Single-Pole Double-Throw) switch capable of switching a complicated RF signal has been in growing demand.
A primary requirement for the SPDT switch is the reduction of high-order harmonic distortions.
As an example of a technology for reducing the high-order harmonic distortions, there has been one which connects FETs (Field Effect Transistors) each composing the SPDT switch in multiple stages (see Patent Document 1).
During the transmission of power from a transmission circuit toward an antenna via the SPDT switch, the FETs which are respectively connected to a reception circuit and to the antenna and are in the OFF state are kept from being turned ON without being influenced by the power from the transmission circuit mentioned above. As a result, the inputted power is outputted to the antenna with no leakage to a reception system and, therefore, a low-loss switch can be implemented.
By connecting the FETs in multiple stages, an RF (Radio Frequency) voltage supplied to each of the FETs in a conducting state is distributed so that the RF voltage per stage, i.e., per FET is reduced advantageously. In other words, it can be said that the RF voltage supplied to the source-to-drain resistance (hereinafter referred to as the ON-state resistance) of each of the FETs in the conducting state can be reduced.
As a result, the gate-to-source capacitance (Cgs), the gate-to-drain capacitance (Cgd), and the RF voltage supplied to the ON-state resistance, each forming a factor causing the harmonic distortions, is reduced and, therefore, the harmonic distortions can be reduced.
As an improvement method for further reducing the harmonic distortions by adopting a multi-gate configuration, there has been a technology which uses a circuit provided with a line for supplying a potential at the midpoint between the two gates of a dual-gate FET (see Patent Document 2). This allows the stabilization of an intermediate potential and thereby allows reductions in harmonic distortions.
In accordance with another improvement method for reducing the harmonic distortions by adopting the multi-gate configuration, an amount of potential lowering due to a leakage current is reduced by changing a line for supplying a potential at the midpoint between the two gates of a dual-gate FET, so that the harmonic distortions are improved successfully (see Patent Document 3).
In addition, there is also a typical SPDT switch based on the above-mentioned circuit technologies according to Patent Documents 1 to 3, in which a voltage booster circuit is provided for further reductions in distortions.
The voltage booster circuit is connected to each of the respective gates of FETs connected between a transmission circuit and an antenna. When any of the FETs is turned ON, the RF power from the FET is inputted to the voltage booster circuit. The voltage booster circuit generates a boosted voltage (about 4.5 V) higher than a control voltage (about 2 V) and applies the boosted voltage to the gate of the FET.
The boosted voltage is also applied to the drains (sources) of the other FETs each in the OFF state via the gate of the FET that has been turned ON. Since each of the gates of the FETs in the OFF state is at a reference potential VSS (0 V), the gate-to-source (−drain) voltage Vgs (Vgd) of each of these FETs becomes negative (to about −4.5 V).
As a result, each of the FETs is brought into a deeper OFF state so that the gate-to-source capacitance (Cgs) and the gate-to-drain capacitance (Cgd) are reduced. This allows reductions in harmonic distortions.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 8(1996)-70245
[Patent Document 2] Japanese Patent Application No. 2004-353715
[Patent Document 3] Japanese Patent Application No. 2005-181669